1. Field of the Invention
The invention generally relates to memory technology. In particular, the invention relates to non-volatile magnetic memory.
2. Description of the Related Art
Computers and other digital systems use memory to store programs and data. A common form of memory is random access memory (RAM). Many memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices, are volatile memories. A volatile memory loses its data when power is removed. For example, after a conventional personal computer is powered off, the volatile memory is reloaded upon a boot up. In addition, certain volatile memories, such as DRAM devices, require periodic refresh cycles to retain their data even when power is continuously supplied.
In contrast to the potential loss of data encountered in volatile memory devices, nonvolatile memory devices retain data for long periods of time when power is removed. Examples of nonvolatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, and the like. Disadvantageously, conventional nonvolatile memories are relatively large, slow, and expensive. Further, many types of conventional semiconductor nonvolatile memories arm relatively limited in write cycle capability and typically can only be programmed to store data about 10,000 times in a particular memory location. This prevents a conventional non-volatile memory device, such as a flash memory device, from being used as general purpose memory.
An alternative memory device is known as magnetoresistive random access memory (MRAM). An MRAM device uses magnetic states to retain data in its memory cells. Advantageously, MRAM devices are relatively fast, are nonvolatile, consume relatively little power, and do not suffer from a write cycle limitation. There are at least three different types of MRAM devices, including giant magneto-resistance (GMR) MRAM devices, magnetic tunnel junction (MTJ) or tunneling magneto-resistance (TMR) MRAM devices, and pseudo spin valve (PSV) MRAM devices. GMR MRAM devices separate at least two ferromagnetic layers with a metallic layer. In a MTJ MRAM device, at least two ferromagnetic layers are separated by a thin insulating tunnel barrier. A PSV MRAM device uses an asymmetric sandwich of the ferromagnetic layers and metallic layer as a memory cell, and the ferromagnetic layers are driven so that they do not switch at the same time.
An interface circuit detects and latches the memory state of a magnetic memory cell so that the contents of the cell can be provided to another circuit, such as a central processing unit (CPU). Disadvantageously, conventional circuits that latch the state of the magnetic memory cell are relatively sensitive to variations in transistor parameters such as gate length. These sensitivities can disadvantageously increase production costs and can also cause data to be incorrectly read from the magnetic memory cell. Embodiments of the invention solve these and other problems by providing a latching circuit that is relatively less sensitive to variations in transistor parameters.
The invention relates to techniques to read a stored state in a magnetoresistive random access memory (MRAM) memory device. Advantageously, an interface circuit or latching circuit according to an embodiment of the invention is relatively insensitive to transistor parameter variations, such as gate length. This advantageously allows the interface circuit to be manufactured less expensively and also allows the interface circuit to reliably detect logic states with relatively small differences in resistance.
A bit line in an MRAM device is segmented into a first portion and a second portion. An interface circuit compares the resistance associated with a first portion and a second portion of a first bit line to the resistance associated with a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit to allow the circuit to achieve a balanced state by coupling outputs of the interface circuit to a relatively low resistance. Decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.
One embodiment according to the invention includes an MRAM memory latching circuit that includes a reset circuit, a first n-type transistor, a second n-type transistor, a first p-type transistor, and a second p-type transistor. The memory latching circuit can be used to latch the stored state of a corresponding memory cell and can also be used as an interface between the memory cell and another device, such as a central processing unit (CPU). The reset circuit includes a first terminal, a second terminal, and a third terminal. The reset circuit couples the second terminal to the third terminal in response to a first state of an input signal applied to the first terminal, and the reset circuit decouples the second terminal from the third terminal in response to a second state of the input signal applied to the first terminal. Coupling of the second terminal to the third terminal effectively disables cross-coupled feedback across the memory latching circuit. The first n-type transistor includes a source coupled to a first portion of a first bit line. The second n-type transistor includes a source coupled to a first portion of a second bit line. The first p-type transistor includes a source coupled to a second portion of the second bit line, where a drain of the first p-type transistor is coupled to a drain of the first n-type transistor and to a first output. A gate of the first p-type transistor is coupled to a gate of the first n-type transistor, to a drain of a second n-type transistor, to a drain of a second p-type transistor, and to the second terminal of the reset circuit. The second p-type transistor includes a source coupled to a second portion of the first bit line, where the drain of the second p-type transistor is coupled to the drain of the second n-type transistor and to a second output. A gate of the second p-type transistor is coupled to a gate of the second n-type transistor, to the drain of the first n-type transistor, to the drain of the first p-type transistor, and to the third terminal of the reset circuit. In one embodiment, the transistors are metal-oxide semiconductor field-effect transistors (MOSFETs).
Another embodiment according to the invention includes an MRAM latching circuit. The latch includes a first terminal adapted to couple to a first portion of a first bit line, a second terminal adapted to couple to a second portion of the first bit line, a third terminal adapted to couple to a first portion of a second bit line, and a fourth terminal adapted to couple to a second portion of the second bit line. The memory latching circuit further includes an input terminal adapted to receive a reset signal, where a first state of the reset signal couples a first output to a second output, and where a second state of the reset signal decouples the first output from the second output so that the first output and the second output latch in opposite directions in response to an imbalance in resistance between the first bit line and the second bit line.
Another embodiment according to the invention includes a bit line in an MRAM. The bit line includes a first portion and a second portion coupled to magnetically sensitive resistors. The first portion is adapted to couple to a voltage source and to an interface circuit The second portion is adapted to couple to a voltage reference (e.g., ground) and to the interface circuit. The first portion is electrically connected to the second portion through the interface circuit. In one embodiment, the first portion and the second portion contain about the same number of magnetically sensitive resistors.
Another embodiment according to the invention includes an MRAM device. The MRAM device includes a plurality of word lines and a plurality of bit lines. A bit line in the plurality of bit lines is coupled to a first portion of magnetically sensitive resistors and is also coupled to a second portion of magnetically sensitive resistors. A memory state of a cell in the MRAM device can be determined by passing a first current through a corresponding word line and a second current through at least one corresponding bit line. Where the MRAM device is a GMR, a corresponding bit line is lower in resistance when a magnetic field in a hard layer of the cell is aligned with a field induced by the first current and the second current than when the magnetic field is not aligned. The number of resistors coupled to first portions and second portions of bit lines can be the same. In one embodiment, at least one pair of bit lines is coupled to a different number of resistors in the corresponding first portion and second portion than another pair of bit lines.
One embodiment according to the invention includes a method of determining a magnetic state in an MRAM cell. The method includes applying a reset signal to an interface circuit such that at least one output of the interface circuit is reset to a balanced state, removing the reset signal, comparing an amount of resistance associated with a first portion of a first bit line to an amount of resistance associated with a first portion of a second bit line, comparing an amount of resistance associated with a second portion of the first bit line to an amount of resistance associated with a second portion of the second bit line, and generating an output with a logic state corresponding to the magnetic state stored in the cell based on the comparisons.
Another embodiment according to the invention includes a method of latching a magnetic state in an MRAM cell, such as a GMR cell. The method includes applying current to a word line corresponding to the MRAM cell. In a rest state, the method includes neutralizing cross-coupled feedback of an interface circuit to allow the interface circuit to balance in response to current applied through first and second portions of a first bit line and through first and second portions of a second bit line, where the current applied to the first bit line and the current applied through the second bit line are substantially equal, and where the first bit line corresponds to the MRAM cell. In a latched state, the method includes enabling cross-coupled feedback across the interface circuit that allows an imbalance in resistance from a stored state of the cell to latch the cell in a corresponding logical state.